The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) devices necessitate design rules of 0.18 .mu.m and below, such as 0.15 .mu.m and below, with increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional contact and interconnection technology, including conventional photolithographic, etching, and deposition techniques.
As a result of the ever-increasing demand for large-scale and ultra-small dimensioned integrated semiconductor devices, self-aligned techniques have become the preferred technology for forming such devices in view of their simplicity and capability of high-density integration. As device dimensions decrease in the deep sub-micron range, both vertically and laterally, many problems arise, especially those caused by an increase in sheet resistance of the contact areas to the source and drain regions and junction leakage as junction layer thickness decreases. To overcome this problem, the use of self-aligned, highly electrically conductive refractory metal suicides, i.e., salicides, has become commonplace in the manufacture of integrated circuit semiconductor devices comprising, e.g., MOS type transistors. Another technique employed in conjunction with refractory metal silicide technology is the use of lightly-doped source and drain extensions formed just at the edge of the gate region, while more heavily-doped source and drain regions, to which ohmic contact is to be provided, are laterally displaced away from the gate by provision of sidewall spacers on opposing sides of the gate electrode.
Salicide processing involves deposition of a metal that forms an intermetallic compound with silicon, but does not react with silicon oxides, nitrides, or oxynitrides under normal processing conditions. Refractory metals commonly employed in salicide processing include platinum (Pt), titanium (Ti), nickel (Ni), and cobalt (Co), each of which forms very low resistivity phases with silicon (Si), e.g., PtSi.sub.2, TiSi.sub.2, NiSi, and CoSi.sub.2. In practice, the refractory metal is deposited in uniform thickness over all exposed upper surface features of a Si wafer, preferably by means of physical vapor deposition (PVD) from an ultra-pure sputtering target and an ultra-high vacuum, multi-chamber DC magnetron sputtering system. In MOS transistor formation, deposition is generally performed after gate etch and source/drain junction formation. In a less common variant, source/drain junction formation is effected subsequent to refractory metal layer deposition via dopant diffusion through the refractory metal layer into the underlying semiconductor. In either case, after deposition, the refractory metal layer blankets the top surface of the gate electrode, typically formed of heavily-doped polysilicon, the silicon oxide, nitride, or oxynitride sidewall spacers on the opposing side surfaces of the gate electrode, the silicon oxide isolation regions formed in the silicon substrate between adjacent active device regions, and the exposed surfaces of the substrate where the source and drain regions are formed or will be subsequently formed. As a result of thermal processing, e.g., a rapid thermal annealing process (RTA) performed in an inert atmosphere, the refractory metal reacts with underlying Si to form electrically conductive silicide layer portions on the top surface of the polysilicon gate electrode and on the exposed surfaces of the substrate where source and drain regions are or will be formed. Unreacted portions of the refractory metal layer, e.g., on the silicon oxide, nitride, or oxynitride sidewall spacers and the silicon oxide isolation regions, are then removed, as by a wet etching process selective to the metal silicide portions. In some instances, e.g., with Co, a first RTA step may be performed at a relatively lower temperature in order to form first-phase CoSi which is then subjected to a second RTA step performed at a relatively high temperature to convert the first-phase CoSi to second-phase, lower resistivity CoSi.sub.2.
Illustrated in FIGS. 1(A)-1(E) are steps in a typical salicide process, illustratively CoSi.sub.2, for manufacturing MOS transistors and CMOS devices according to one process scheme of the conventional art. The term "semiconductor substrate" as employed throughout the present disclosure and claims, denotes a Si-containing wafer, e.g., a monocrystalline Si wafer, or an epitaxial Si-containing layer formed on a semiconductor substrate and comprising at least one region 1 of a first conductivity type. It will be appreciated that for P-MOS transistors, region 1 is n-type and for N-MOS transistors, region 1 is p-type. It is further understood that the substrate may comprise pluralities of n- and p-type regions arrayed in a desired pattern, as, for example, in CMOS devices.
Referring more particularly to FIG. 1(A), reference numeral 1 indicates a region or portion of a Si-containing semiconductor substrate of a first conductivity type (p or n), fabricated as a MOS transistor precursor 2 for use in a salicide process scheme. Precursor 2 is processed, as by conventional techniques not described here in detail, in order to not unnecessarily obscure the primary significance of the following description. Precursor 2 comprises a plurality of, illustratively two, isolation regions 3 and 3' of a silicon oxide, e.g., shallow trench isolation (STI) regions, extending from the substrate surface 4 to a prescribed depth below the surface. A gate insulator layer 5, typically comprising a silicon oxide layer about 25-50 .ANG. thick, is formed on substrate surface 4. Gate electrode 6, typically of heavily-doped polysilicon, is formed over a portion of silicon oxide gate insulator layer 5, and comprises opposing side surfaces 6', 6', and top surface 6". Blanket layer 7 of an insulative material, typically an oxide, nitride, or oxynitride of silicon, is then formed to cover all exposed portions of substrate surface 4 and the exposed surfaces of the various features formed thereon or therein, inter alia, the opposing side surfaces 6', 6' and top surface 6" of gate electrode 6 and the upper surface of STI regions 3, 3'. The thickness of blanket insulative layer 7 is selected so as to provide sidewall spacers 7', 7' of desired width (see below) on each of the opposing side surfaces 6', 6' of the gate electrode 6.
Referring now to FIG. 1(B), MOS precursor structure 2 is then subjected to an anisotropic etching process, as by reactive plasma etching utilizing a fluorocarbon- or fluorohydrocarbon-based plasma comprising argon (Ar) and at least one reactive gaseous species selected from CF.sub.4 and CHF.sub.3, for selectively removing the laterally extending portions of insulative layer 7 and underlying portions of the gate oxide layer 5, whereby sidewall spacers 7', 7' of desired width profile are formed along the opposing side surfaces 6', 6' of gate electrode 6.
Adverting to FIG. 1(C), moderately- to heavily-doped source and drain junction regions 8 and 9 of conductivity type opposite that of the substrate or epitaxial layer on a suitable substrate are then formed in substrate region 1, as by conventional ion implantation (the details of which are omitted for brevity), with sidewall spacers 7', 7' acting as implantation masks and setting the lateral displacement length of moderately- to heavily-doped source/drain regions 8 and 9 from the respective proximal edges 6', 6' of gate electrode 6.
With reference to FIG. 1(D), in a following step, the structure thus-formed with implanted moderately- to heavily-doped source/drain regions 8, 9 is subjected to a conventional high temperature treatment, typically rapid thermal annealing (RTA), for effecting activation and diffusion of the implanted dopant species, thereby also forming lightly doped, shallower depth source/drain extension regions 8', 9' laterally extending from the respective proximal edges of the moderately- to heavily-doped source/drain regions 8, 9 to just beneath the neighboring edge 6' of gate electrode 6. The above-described method for forming source/drain regions including lightly-doped extensions is merely illustrative: i.e., equivalent source/drain structures may be formed by alternative process schemes, e.g., by first lightly implanting substrate 1 with dopant impurities of second conductivity type, with the implanted regions extending to just beneath the respective edges of the gate electrode, followed by selective heavy implantation of the lightly-doped implant to form heavily-doped source/drain regions appropriately spaced from the gate electrode by the lightly-doped (extension) implants.
With continued reference to FIG. 1(D), a layer 10 of a refractory metal metal, typically Pt, Co, Ni, or Ti, is then formed, as by DC sputtering, to cover the exposed upper surfaces of precursor 2. Following refractory metal layer 10 deposition, a thermal treatment, typically rapid thermal annealing (RTA), is performed at a temperature and for a time sufficient to convert metal layer 10 to the corresponding electrically conductive metal silicide, e.g., PtSi.sub.2, CoSi.sub.2, NiSi, or TiSi.sub.2. Since the refractory metal silicide forms only where metal layer 10 is in contact with the underlying silicon, the unreacted portions of metal layer 10 formed over the silicon oxide isolation regions 3 and 3' and silicon nitride sidewall spacers 7, 7' are selectively removed, as by a wet etch process.
Referring now to FIG. 1(E), the resulting structure after reaction and removal of unreacted metal comprises metal silicide layer portions 11 and 12, 12' respectively formed over gate electrode 6 and heavily-doped source and drain regions 8 and 9. Further processing may include, inter alia, formation of metal contact and dielectric insulator layers. However, as is evident from FIG. 1(E), the lower surfaces of the metal silicide layer 12, 12' portions formed by the above-described methodology are rough at the silicide-silicon interfaces, disadvantageously resulting in penetration of the underlying silicon substrate 1 by the silicide portions 12, 12'. Such penetration or "spiking" of the silicon in the region below the source and drain junction regions 8 and 9, illustratively shown at 13 and 13', can cause local shorting of the junctions, thereby resulting in junction leakage. The effect of junction penetration or spiking is greatest with metals such as Co, which have relatively high silicon consumption ratios. Junction penetration or spiking can be moderated or at least minimized and improved junction integrity provided by increasing the junction depth of source and drain regions 8 and 9 or by providing a thinner refractory metal layer, thereby reducing silicon consumption during silicidation. However, neither of these alternatives is satisfactory: the former approach runs counter to the trend toward smaller device dimensions, both vertically and laterally, in order to increase transistor switching speeds, and the latter approach results in an increase in metal silicide sheet resistance attendant its decrease in thickness.
A number of techniques for reducing leakage in ultra-shallow junctions employed in MOSFET type semiconductor devices have been proposed, such as are disclosed in U.S. Pat. Nos. 4,835,112; 5,208,472; 5,536,684; and 5,691,212. Such techniques, however, materially add to process complexity and include such steps as germanium implantation to retard dopant diffusion, provision of multiple dielectrics at the edges of the gate electrode, formation of a CoSi.sub.2 --TiN.sub.x, bi-layer followed by removal of the TiN.sub.x layer and ion implantation of the remaining CoSi.sub.2 layer, and formation of an amorphous silicon layer on a silicon MOS precursor and subsequent implantation, oxidation, annealing, etc., steps.
Thus, there exists a need for a simplified methodology for forming self-aligned silicide (i.e., salicide) contacts to ultra-thin transistor source and drain regions which provide low contact sheet resistance, absence of spiking, at least minimal junction leakage, and easy compatibility with conventional process flow for the manufacture of MOS-based semiconductor devices, e.g., CMOS devices. Moreover, there exists a need for an improved process for fabricating high quality, low junction leakage MOS transistor-based devices which provides increased manufacturing throughput and product yield.